The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating a semiconductor device with a vertical channel.
A channel length of a transistor decreases as the integration of a semiconductor device increases. However, the decreased channel length of the transistor causes a short channel effect such as a drain induced barrier lowering (DIBL) phenomenon, a hot carrier effect, and a punch-through. To remove the short channel effect, various methods have been suggested such as decreasing a depth of a junction region and increasing a relative channel length by forming a recess in a channel region of the transistor.
However, as an integration density of a semiconductor memory device, particularly, a dynamic random access memory (DRAM), approaches giga bits, fabrication of a smaller transistor is required. In other words, the giga-bit scale DRAM transistor requires a device dimension under 8F2 (where F is a minimum feature size), and further, a device dimension size of about 4F2. Therefore, an existing planar transistor structure having a gate electrode over a substrate and junction regions on both sides of the gate electrode does not satisfy a required device dimension even though the channel length is scaled.
To overcome the above limitations, a vertical channel transistor has been introduced. A typical structure of a vertical channel transistor is disclosed in U.S. Patent Publication No. 2006-0097304 and Korean Patent No. 0723527.
FIG. 1 is a perspective view of a semiconductor device employing a conventional vertical channel transistor and FIG. 2 is a top view of the semiconductor device of FIG. 1.
Referring to FIGS. 1 and 2, a plurality of pillars P are formed over a substrate 100. The pillars include a substrate material and are arrayed in a first direction X-X′ and a second direction Y-Y′ crossing the first direction. The pillars are formed by etching the substrate 100 using a hard mask pattern (not shown).
One side of a unit cell region C has a feature size of 2F, i.e., a pitch in the first direction of the hard mask pattern, where F is the minimum feature size. The other side of the unit cell region C has a feature size of 2F, i.e., a pitch in the second direction of the hard mask pattern. As a result, a square feature size of the unit cell region C becomes 4F2. Even though the hard mask pattern has a square form, the pillar P is formed to have a cylindrical structure as the etch process proceeds.
A bit line 101, which extends in the first direction while surrounding corresponding pillars, is formed in the substrate 100 between each pair of neighboring pillars arranged in the first direction. The bit line 101 is divided by a device isolation trench T.
For each pillar P, a gate electrode (not shown) is formed on a circumferential surface of the pillar P to surround the pillar P. A word line 102 electrically connected to the surrounding gate electrode and extending in the second direction is formed.
A storage electrode 104 is formed over the pillar P. A contact plug 103 is interposed between the pillar P and the storage electrode 104.
When fabricating this semiconductor device, since the channel is formed vertical to the substrate surface, it is possible to increase the channel length regardless of the device dimension, resulting in prevention of the short channel effect. Also, since the gate electrode is formed surrounding the circumferential surface of the pillar P, a channel width of the transistor is increased and, thus, an operation current of the transistor is improved.
However, in a process of forming the contact plug 103 and the storage electrode 104 over the pillar P, a limitation on the process occurs and causes device failure. This limitation is explained in detail referring to FIGS. 3A to 3D, hereinafter.
FIGS. 3A to 3D are cross-sectional views of a method for fabricating the semiconductor device employing a conventional vertical channel transistor. Particularly, FIGS. 3A to 3D are cross-sectional views obtained from FIGS. 1 and 2 in the second direction. These figures are for explaining limitations in the process of forming the contact plug and the storage electrode over the pillar and, therefore, a detailed description of unrelated parts is omitted.
FIG. 3A shows a substrate structure including a substrate 300 having a plurality of pillars arranged in the first and the second directions. A hard mask pattern 305 is formed over each pillar P. A bit line 301 is extended in the first direction while surrounding the pillar P in the substrate 300 between a pair of neighboring pillars arranged in the first direction and divided by a device isolation trench T. A first insulation layer 303 fills a part of the trench T. A gate electrode 304 surrounds a circumferential surface of a lower portion of the pillar P. A word line 302 extends in the second direction and connects to the surrounding gate electrode 304.
Referring to FIG. 3B, a second insulation layer 306 is formed over the resultant structure of FIG. 3A and is planarized through, e.g., by a chemical mechanical polishing (CMP) process, until the hard mask pattern 305 is exposed.
Referring to FIG. 3C, an opening unit 307 is formed by selectively removing the exposed hard mask pattern 305 to expose a surface of the pillar P. Since the hard mask pattern 305 generally includes a nitride layer, the removal of the hard mask pattern 305 is performed by a wet etch using, e.g., a phosphoric acid.
Although not shown, a spacer and a pad layer including an oxide layer are formed on a sidewall and a lower portion of the hard mask pattern 305, respectively. Therefore, after the hard mask pattern 305 is removed, processes for removing the spacer and the pad layer are performed to expose the surface of the pillar P.
Referring to FIG. 3D, a plug material is filled in the opening unit 307 to form a contact plug 308 that is electrically connected to the pillar P.
Then, a storage electrode (not shown) is formed over the contact plug 308.
In the above process, when performing the wet etch process using the phosphoric acid, a possibility of damaging the spacer made of the oxide layer on the sidewall increases. When the spacer is damaged, in a subsequent process for removing the spacer and the pad layer, the second insulation layer 306 may also be damaged. Thereafter, an electrical short between the contact plug 308 and the word line 302 or the surrounding gate electrode 304 may occur and cause device failure.
Also, after removing the hard mask pattern 305, forming the contact plug 308 and the storage electrode in the remaining space may complicate the method for fabricating the semiconductor device.